The present invention relates to semiconductor devices having a field effect transistor and methods for manufacturing the same, and more particularly, to semiconductor devices having a gate electrode that is formed from two or more layers and methods for manufacturing the same.
Currently, there is a technique in which a gate electrode 230 of a MOS transistor 300 shown in FIG. 14(b) is formed by a so-called damascene method. One example of a method for manufacturing a MOS transistor 300 using a technique in which its gate electrode 230 is formed by a damascene method is described below.
As shown in FIG. 13(a), a gate dielectric layer 220 (also sometimes referred to as a gate insulation layer) and a dummy electrode 232 are formed on a silicon substrate 210. Next, the dummy electrode 232 is patterned. Then, a low concentration impurity diffusion layer 242 is formed in the silicon substrate 210 on the sides of the dummy electrode 232. Next, an insulation layer is formed over the entire surface, and the insulation layer and the gate dielectric layer 220 are etched by RIE to form a sidewall spacer 250 on the side wall of the dummy electrode 232. Then, a high concentration impurity diffusion layer 244 is formed in the silicon substrate 210 on the side of the sidewall spacer 250.
Next, as shown in FIG. 13(b), an insulation layer 260 is formed on the silicon substrate 210, and the insulation layer 260 is then planarized to expose the dummy electrode 232.
Next, as shown in FIG. 14(a), the entire dummy electrode 232 is removed to form a through hole 270.
Next, as shown in FIG. 14(b), a metal layer is formed in a manner to fill the through hole 270, and the metal layer is then etched-back to form a gate electrode 230.
Techniques to form gate electrodes by a damascene method are described in references such as U.S. Pat. No. 5,960,270, U.S. Pat. No. 5,391,510 and U.S. Pat. No. 5,434,093.
Embodiments include a method for manufacturing a semiconductor device, the method including the steps of: (a) forming a gate dielectric layer on a semiconductor layer; (b) forming a first conduction layer having a specified pattern on the gate dielectric layer; (c) forming sidewall insulation layers on side walls of the first conduction layer; (d) forming a source region and a drain region in the semiconductor layer; (e) depositing a first insulation layer that covers the first conduction layer and the sidewall insulation layers, the first insulation layer comprising a material different from that of the sidewall insulation layers; (f) planarizing the first insulation layer until an upper surface of the first conduction layer is exposed; (g) removing a part of the first conduction layer in a manner that the gate dielectric layer is not exposed to thereby form a recessed section on the first conduction layer between the sidewall insulation layers; (h) partially filling a second conduction layer in the recessed section to form a gate electrode that includes at least the first conduction layer and the second conduction layer; (i) forming a second insulation layer at the recessed section on the second conduction layer, the second insulation layer being composed of a material different from that of the first insulation layer; (j) etching the first insulation layer to form a first through hole that reaches the source region or the drain region; and (k) forming a first contact layer in the first through hole.
Embodiments also include a method for manufacturing a semiconductor device, including forming a gate dielectric layer on a semiconductor layer and forming a first conduction layer having a specified pattern on the gate dielectric layer. Sidewall insulation layers are formed on side walls of the first conduction layer. A source region and a drain region are formed in the semiconductor layer. A part of the first conduction layer is removed in a manner so that the gate dielectric layer is not exposed, to thereby form a recessed section on the first conduction layer between the sidewall insulation layers. The removing a part of the first conduction layer is carried out after formation of the source region and the drain region. The method also includes forming a second conduction layer in a portion of the recessed section, and forming an insulation layer in the recessed section on the second conduction layer.
Embodiments also include semiconductor device including a field effect transistor, the field effect transistor including a gate dielectric layer, a gate electrode, a source region and a drain region. The device includes a second insulation layer formed on the gate electrode and sidewall insulation layers formed on side walls of the gate electrode. A first insulation layer is formed on the sides of sidewall insulation layers. The gate electrode includes a first conduction layer and a second conduction layer, the first conduction layer being formed on the gate dielectric layer, and the second conduction layer being formed above the first conduction layer. A first through hole reaching the source region or the drain region is formed in the first insulation layer. A first contact layer is formed in the first through hole. As the thickness of the first conduction layer is compared based on a top surface of the gate dielectric layer, the first conduction layer has thickness that gradually becomes greater from a central section thereof toward the side walls.
Embodiments also include a semiconductor device including a field effect transistor, the field effect transistor including a gate dielectric layer, a gate electrode, a source region and a drain region. The device includes a second insulation layer formed on the gate electrode, and sidewall insulation layers formed on side walls of the gate electrode. A first insulation layer is formed on the sides of sidewall insulation layers. The gate electrode includes a first conduction layer and a second conduction layer, the first conduction layer being formed on the gate dielectric layer, and the second conduction layer being formed above the first conduction layer. A first through hole reaching the source region or the drain region is formed in the first insulation layer. A first contact layer is formed in the first through hole. As the thickness of the first conduction layer is compared based on a top surface of the gate dielectric layer, an end portion of the first conduction layer has a greater thickness as compared to a thickness at a central section.